title={Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications},
author={Doosan Cho and Pasricha, S. and Issenin, I. and Dutt, N.D. and Minwook Ahn and Yunheung Paek},
journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
month={April },
abstract={Exploiting runtime memory access traces can be a complementary approach to compiler optimizations for the energy reduction in memory hierarchy. This is particularly important for emerging multimedia applications since they usually have input-sensitive runtime behavior which results in dynamic and/or irregular memory access patterns. These types of applications are normally hard to optimize by static compiler optimizations. The reason is that their behavior stays unknown until runtime and may even change during computation. To tackle this problem, we propose an integrated approach of software [compiler and operating system (OS)] and hardware (data access record table) techniques to exploit data reusability of multimedia applications in Multiprocessor Systems on Chip. Guided by compiler analysis for generating scratch pad data layouts and hardware components for tracking dynamic memory accesses, the scratch pad data layout adapts to an input data pattern with the help of a runtime scratch pad memory manager incorporated in the OS. The runtime data placement strategy presented in this paper provides efficient scratch pad utilization for the dynamic applications. The goal is to minimize the amount of accesses to the main memory over the entire runtime of the system, which leads to a reduction in the energy consumption of the system. Our experimental results show that our approach is able to significantly improve the energy consumption of multimedia applications with dynamic memory access behavior over an existing compiler technique and an alternative hardware technique.},
keywords={digital storage, microprocessor chips, program compilers, system-on-chipadaptive scratch pad memory management, compiler, compiler optimizations, data reusability, energy reduction, memory hierarchy, multimedia applications, multiprocessor systems on chip, runtime memory access},