Deploying Formal in a Simulation World

Abstract

Abstract. Missing bugs in hardware designs is expensive enough that the semiconductor industry routinely spends 2/3 of the design cycle in verifying the designs before tapeout. Formal verification technology is a mathematical way of verifying designs, that are so far impossible to verify with conventional simulation-based methods in a given design schedule. However, the adoption of formal in a chip design schedule requires carefully integrating planning, execution and coverage targets with the traditional simulation-based sign-off metrics. In this talk, we describe how formal verification has evolved, and how it has recently changed the world of IC design and verification, at companies like Intel, Samsung, Qualcomm, Broadcom, NVIDIA and Huawei.

Short bio

Bio: Vigyan Singhal is the CEO of Oski Technology, which specializes in applying formal verification on hardware designs. oski is headquarted in the Silicon Valley with an office in New Delhi, India. Oski is the leader in the formal verification methodology, and has won many best paper awards for its work at leading conferences. Vigyan was previously the founder and CEO of two VC-funded startups: Jasper Design Automation in EDA, and Elastix in low-power semiconductors. Vigyan has a PhD from UC Berkeley and a BTech in Computer Science from IIT Kanpur, where he graduated at the top of his class.

Resources

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